This invention is related generally a method of making a semiconductor device and specifically to a dual damascene process using a silicon containing imaging layer.
In order to increase the miniaturization of semiconductor devices, contacts between conductive layers in a semiconductor device are formed by the dual damascene process which utilizes a dual inlaid via. An example of the xe2x80x9cvia firstxe2x80x9d dual damascene process is illustrated in FIGS. 1A-F.
FIG. 1A illustrates a portion of an in process metallization section 1 of a semiconductor device. The metallization section contains a first conductive layer 3 and an insulating layer 5 formed over the first conductive layer 3. The conductive layer 3 may be a metal interconnect, such as an aluminum interconnect. The insulating layer 5 contains a narrow via 7 which extends from the top surface 9 of the insulating layer 7 to the first conductive layer 3. The via 7 has a circular cross section and contains only one sidewall 11 having a circular perimeter.
A conventional, organic polymer photoresist layer 13 having a carbon backbone, such as a positive novolac photoresist layer, is formed in the via 7 and over the upper surface 9 of the insulating layer 5, as shown in FIG. 1B. The photoresist layer 13 is selectively exposed to radiation through a conventional lithographic mask or reticle (not shown), as illustrated in FIG. 1C. During the exposure, a first portion 15 of the photoresist layer 13 over the upper surface 9 of the insulating layer 5 directly adjacent to via 7 sidewall 11 and a second portion 17 of the photoresist layer 13 in the via 7 are exposed, as indicated by the cross hatching in FIG. 1C. A third portion 19 of the photoresist layer over the upper surface 9 of the insulating layer 5 distal from the via sidewall 11 is shielded by the mask and is not exposed to radiation. The exposed positive photoresist is then patterned to remove the exposed first and second photoresist portions 15, 17 while leaving the third portion 19 of the photoresist layer 13 on the insulating layer 5 as a mask, as illustrated in FIG. 1D.
The exposed upper surface 9 of the insulating layer 5 is etched using the third portion 19 of the photoresist layer 13 as a mask to form a trench 21 having a width greater than that of the via 7. The third portion 19 of the photoresist layer 13 is removed by conventional techniques, such as ashing, to form a structure illustrated in FIG. 1E. The top of the via 7 is located in a bottom surface 23 of the trench 21. In other words, the exposed portion of the insulating layer 5 is etched to remove a top section of the exposed portion of the insulating layer, without etching the bottom section of the exposed portion.
The dual damascene process is then completed by forming a second conductive layer 25, as illustrated in FIG. 1F. The second conductive layer 25 may be a metal layer which is formed in the trench 21, such that it extends through the via 7 to contact the first conductive layer 3. The second conductive layer is planarized by chemical mechanical polishing or etch back such that its top surface is even with the upper surface 9 of the insulating layer 5.
However, the prior art dual damascene process suffers from a problem of via poisoning. This problem is illustrated in FIG. 2. During the photoresist exposure step illustrated in FIG. 1C, the second portion 17 of the photoresist layer 13 binds to the via 7 sidewall 11 and forms a rigid mushroom shape, especially when the via 7 width is small, as shown in FIG. 2. Therefore, the second portion 17 of the photoresist layer 13 cannot be removed from the via 7 during subsequent developing and ashing steps because it is chemically and/or physically bound to the via sidewall 11. Thus, the second conductive layer 25 cannot contact the first conductive layer 3 through the via 7 because the via 7 is filled by the second portion 17 of the photoresist layer which is rigidly bound to the via 7 sidewall 11. This causes an open circuit between the first and second conductive layers which leads to device failure. This poison via problem is especially severe when the insulating layer 5 is a low-k (i.e., a low dielectric constant) polymer material, such as hydrogensilsesquioxane (HSQ).
According to one aspect of the present invention, there is provided a method of making a dual inlaid via in a first layer, comprising forming a first opening in the first layer, forming an inorganic base radiation sensitive layer in the first opening, selectively exposing the inorganic base radiation sensitive layer to radiation, patterning the exposed inorganic base radiation sensitive layer, and forming a second opening in communication with the first opening using the patterned inorganic base radiation sensitive layer as a mask.
According to another aspect of the present invention, there is provided a method of making a semiconductor device containing a dual inlaid via, comprising forming a via in a polymer containing insulating layer, forming a first silicon backbone containing polymer imaging layer in the via in contact with the via sidewall and a bottom surface of the via and over an upper surface of the insulating layer and selectively exposing the imaging layer to radiation. The method further comprises patterning the exposed first imaging layer to remove a first portion of the first imaging layer from the upper surface of the insulating layer directly adjacent to via sidewall and a second portion of the first imaging layer in contact with the via sidewall and the bottom surface of the via, while leaving a third portion of the first imaging layer over the upper surface of the insulating layer distal from the via sidewall, and etching an exposed upper portion of the insulating layer using the third portion of the imaging layer as a mask to form a trench having a width greater than that of the via, such that a top of the via is located in a bottom surface of the trench.
According to another aspect of the present invention, there is provided a method of making a semiconductor device containing a dual damascene contact, comprising forming an active element over a substrate, forming a first conductive layer over the active element, forming an insulating layer over the first conductive layer and forming a first polysilane imaging layer over the insulating layer. The method further comprises selectively exposing the first imaging layer to radiation, patterning the first imaging layer, and etching the insulating layer using the patterned first imaging layer as a mask to form a via having a first radius extending through the insulating layer to the first conductive layer. The method further comprises removing the first imaging layer, forming a second polysilane imaging layer having a thickness smaller than the first radius in the via in contact with via sidewall and a bottom surface of the via and over an upper surface of the insulating layer, such that the second polysilane imaging layer does not fill an entire volume of the via and selectively exposing a first and a second portions of the second imaging layer to radiation through a mask. The method further comprises patterning the exposed second imaging layer to remove the first portion of the second imaging layer from the upper surface of the insulating layer directly adjacent to the via sidewall and a second portion of the second imaging layer in contact with the sidewall and the bottom surface of the via, while leaving a third portion of the second imaging layer over the upper surface of the insulating layer distal from the via sidewall, etching an exposed upper portion of the insulating layer using the third portion of the second imaging layer as a mask to form a trench having a width greater than that of the via, such that a top of the via is located in a bottom surface of the trench, forming a second conductive layer in the trench such that the second conductive layer contacts the first conductive layer through the via, and planarizing the second conductive layer such that a top surface of the second conductive layer is substantially level with the upper surface of the insulating layer.